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nt512 d72 s 8p abg 512mb : 64m x 72 pc210 0 unbuffered ddr dimm 184pin un buffered ddr dimm w i th ecc based o n ddr 266 3 2 m x 8 sd ram features ? 64mx72 un buff e red dd r dimm based on 32m x8 ddr sdram ? jedec standa rd 184- pin dual i n -line memor y module ? error ch eck correction (ecc ) s upport ? performance: p c 2 1 0 0 speed sort -75t dimm cas late n cy 2 unit f ck c l o c k frequenc y 1 3 3 m h z t ck c l o c k cy c l e 7 . 5 n s f dq dq bu rst freq ue ncy 266 mhz ? intended for 1 3 3 mhz applicatio ns ? inputs and outp u ts are sstl- 2 compatible ? v dd = 2.5volt 0.2, v ddq = 2.5 v olt 0.2 ? sdrams have 4 internal banks for concurrent op eration ? differential clock inputs ? data is read or written on both clock edges ? dram dll aligns dq and dqs trans itions w i th clock transitions ? address and control signals are fully s y nchronous to positive clock edge ? programmable oper ation: - dimm cas l a t enc y : 2, 2.5 - burst t y pe: se quential or interl eave - burst length: 2, 4, 8 - ope r ation: burs t read and w r ite ? auto refresh ( c br) and self r e fresh modes ? automatic and controlled precha rge commands ? 13/10/2 addres sing (ro w / column /bank) ? 7.8 s max. average periodic r e fresh interval ? serial presence detect ? gold contacts ? sdrams in 66-pin tsop t y pe ii package d e s c r i p t i o n nt512d 72s8pa b g is an unbuffe red 184 -pin dou b le data rate (d dr) s y nchronou s dram dual in- l ine memor y mo dule (dimm), organized as a t w o - bank 64m x72 high-speed me mor y a rra y. the module uses eighteen 32m x8 dd r sdrams in 40 0 mil tsop ii packages. these dimms are man u factured using r a w ca rds developed for b r oad ind u str y use as ref e rence designs. the use of these common design files min i mizes e l ectrical variation bet w een supplier s . all nany a dd r sdram dimm s provide a high- performa n ce, flexible 8-b y te interface in a 5.25? long space-savin g footprint. the dimm is inte nded for use in a pplications operating up to 133 m h z clock speeds and achieves hi g h -speed data t r a n sfer rates o f up to 266 mhz. prior t o an y access operation, the device cas latenc y an d burst t y p e / leng th/operation t y pe must be prog ra mmed into the dimm b y a ddres s inputs a0-a12 and i/o inputs b a 0 and ba1 using the mode r egister set c y cle. the dimm uses serial presence- detect implemented via a serial 2,048-bit eeprom using a standard iic protocol. th e first 128 b y t es of serial pd data ar e progr ammed a nd locked during module assembly. th e remaining 128 b y t e s are av ailable for use b y the customer. o r d e r i n g i n f o r m a t i o n part numbe r s p e e d o r g a n i z a t i o n leads pow e r 133mhz (7.5ns @ cl = 2) nt512d 72s8p a b g-75 t 133mhz (7.5ns @ cl = 2.5 ) ddr266 2-2-2 p c 2 1 0 0 6 4 m x 7 2 g o l d 2 . 5 v rev 1.0 1 02/2003 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512 d72 s 8p abg 512mb : 64m x 72 pc210 0 unbuffered ddr dimm pin description ck0, ck1, ck2, ck0 , ck1 , ck2 differential clock inputs dq0 - d q 63 data input/output cke0, cke1 clock enable cb0-cb7 check bit data input/out put ras ro w address str obe dqs0- d qs8 bidirectional data strobes cas column address strobe dm0-dm8 input data mask we write enable v dd p o w e r (2. 5 v ) s0 chip selects v ddq suppl y voltage fo r dqs (2.5v) a0-a9, a11, a12 address inputs v ss g r o u n d a10/ap address input/au t oprecharge nc no connect ba0, ba1 sdram bank address inputs scl serial presence detect clock input reset reset pin sda serial presence detect data inpu t/output v ref ref. voltage for sstl_2 inputs sa0-2 serial presence detect address i nputs v ddid v dd identification flag. v ddspd serial eeprom positive pow er s uppl y (2.5v) p i n o u t p i n f r o n t p i n b a c k p i n f r o n t p i n b a c k pin f r o n t p i n b a c k 1 v ref 9 3 v ss 3 2 a 5 124 v ss 6 2 v ddq 1 5 4 ras 2 d q 0 9 4 d q 4 3 3 d q 2 4 125 a 6 6 3 we 1 5 5 d q 4 5 3 v ss 9 5 d q 5 3 4 v ss 1 2 6 d q 2 8 6 4 d q 4 1 1 5 6 v ddq 4 d q 1 9 6 v ddq 3 5 d q 2 5 127 d q 2 9 6 5 cas 157 s0 5 d q s 0 9 7 d m 0 3 6 d q s 3 128 v ddq 6 6 v ss 1 5 8 s1 6 d q 2 9 8 d q 6 3 7 a 4 129 d m 3 6 7 d q s 5 1 5 9 d m 5 7 v dd 9 9 d q 7 3 8 v dd 1 3 0 a 3 6 8 d q 4 2 1 6 0 v ss 8 d q 3 1 0 0 v ss 3 9 d q 2 6 131 d q 3 0 6 9 d q 4 3 1 6 1 d q 4 6 9 n c 1 0 1 n c 4 0 d q 2 7 132 v ss 7 0 v dd 1 6 2 d q 4 7 1 0 n c 1 0 2 n c 4 1 a 2 133 d q 3 1 7 1 n c 1 6 3 n c 1 1 v ss 1 0 3 n c 4 2 v ss 1 3 4 c b 4 7 2 d q 4 8 1 6 4 v ddq 1 2 d q 8 1 0 4 v ddq 4 3 a 1 135 c b 5 7 3 d q 4 9 1 6 5 d q 5 2 1 3 d q 9 1 0 5 d q 1 2 4 4 c b 0 136 v ddq 7 4 v ss 1 6 6 d q 5 3 1 4 d q s 1 1 0 6 d q 1 3 4 5 c b 1 137 c k 0 7 5 ck2 1 6 7 n c 1 5 v ddq 1 0 7 d m 1 4 6 v dd 1 3 8 ck0 7 6 c k 2 1 6 8 v dd 1 6 c k 1 1 0 8 v dd 4 7 d q s 8 139 v ss 7 7 v ddq 1 6 9 d m 6 17 ck1 1 0 9 d q 1 4 4 8 a 0 140 d m 8 7 8 d q s 6 1 7 0 d q 5 4 1 8 v ss 1 1 0 d q 1 5 4 9 c b 2 141 a 1 0 7 9 d q 5 0 1 7 1 d q 5 5 1 9 d q 1 0 1 1 1 c k e 1 5 0 v ss 1 4 2 c b 6 8 0 d q 5 1 1 7 2 v ddq 2 0 d q 1 1 1 1 2 v ddq 5 1 c b 3 143 v ddq 8 1 v ss 1 7 3 n c 2 1 c k e 0 1 1 3 n c 5 2 b a 1 144 c b 7 8 2 v ddid 1 7 4 d q 6 0 2 2 v ddq 1 1 4 d q 2 0 ke y ke y 8 3 d q 5 6 1 7 5 d q 6 1 2 3 d q 1 6 1 1 5 a 1 2 5 3 d q 3 2 145 v ss 8 4 d q 5 7 1 7 6 v ss 2 4 d q 1 7 1 1 6 v ss 5 4 v ddq 1 4 6 d q 3 6 8 5 v dd 1 7 7 d m 7 2 5 d q s 2 1 1 7 d q 2 1 5 5 d q 3 3 147 d q 3 7 8 6 d q s 7 1 7 8 d q 6 2 2 6 v ss 1 1 8 a 1 1 5 6 d q s 4 148 v dd 8 7 d q 5 8 1 7 9 d q 6 3 2 7 a 9 1 1 9 d m 2 5 7 d q 3 4 149 d m 4 8 8 d q 5 9 1 8 0 v ddq 2 8 d q 1 8 1 2 0 v dd 5 8 v ss 1 5 0 d q 3 8 8 9 v ss 1 8 1 s a 0 2 9 a 7 1 2 1 d q 2 2 5 9 b a 0 151 d q 3 9 9 0 n c 1 8 2 s a 1 3 0 v ddq 1 2 2 a 8 6 0 d q 3 5 152 v ss 9 1 s d a 1 8 3 s a 2 3 1 d q 1 9 1 2 3 d q 2 3 6 1 d q 4 0 153 d q 4 4 9 2 s c l 1 8 4 v ddspd note: all pin assignment s are con s istent for all 8-byte unbuf fe red v e rsions. rev 1.0 2 02/2003 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512 d72 s 8p abg 512mb : 64m x 72 pc210 0 unbuffered ddr dimm i n p u t / o u t p u t f u n c t i o n a l d e s c r i p t i o n s y mbol ty p e polarit y function ck0, ck1, ck2 (sstl) positive edge the positive line of the differential pair of s y stem clock inputs w h ich drives the input to the on-dimm pl l. all the ddr s dram address a nd control inputs are sampled on t he rising edge of the i r associated clo c ks. ck0 , ck1 , ck2 (sstl) negative edge the negative line of the differential pair of s y st em clock inputs w h ich drives the input to the on-dimm pl l. cke0, cke1 (sstl) active high activates the sdram ck signal w h en high and d eactivates the ck signal w hen lo w . b y deactivating the clocks, cke low initiates the pow e r do w n mo de, or the self refresh mode. s0 (sstl) active lo w enables the associated sdram command decode r w hen lo w an d d i sables the command decod er w hen high. w hen the comma n d decoder is disabled, ne w comm ands are ignored but p r evious operation s continue. ras , cas , we (sstl) active lo w when sampled at the positive rising edge of the clock, ras , cas , we define the operation to be e x ecuted b y the s dram. v ref suppl y reference voltag e for sstl - 2 inp u ts v ddq s u p p l y isolated power s uppl y for t he dd r sdram out put buffers to pr ovide improved noise immunity ba0, ba1 (sstl) - selects w h ich sdram bank is to be active. a0 - a9 a10/ap a11, a12 (sstl) - during a bank a c tivate command cy cle, a0-a1 2 d e fines the ro w ad dress (ra0-ra1 2) w h en sampled at the rising clock edge. during a rea d or write command cy cle, a0-a9, a 1 1 defines the column address (ca0-ca1 0) w h e n sampled at the rising clock edge. in addition to th e column addres s, ap is used to invoke autoprechar ge operation at t he end of the bu r s t read or write cy cle. if ap is high, autoprecha rge is selected and ba0/ba1 define the bank to be precharged. if a p is low , autopr e c harge is disable d . during a precha r ge command c y c l e, ap is used in conjunction w i th ba0/ba1 to contr o l w h ich bank(s) t o precharge. if ap is high a ll 4 bank s w ill be precharged rega rdless of the state of ba0/ba1. if ap is low , the n ba0/ba1 are u s ed to define w h ich bank to pre-char ge. dq0 - d q 63 (sstl) - data and ch eck bit input/output p i ns operat e in the same manner a s on conventional drams. dq0 ? dq6 3 cb0 ? cb7 (sstl) active high data and ch eck bit input/output pins. check bits are onl y a pplicable on the x72 di mm configurations. v dd, v ss suppl y pow e r and g r oun d for the d dr s dram input buff e rs and core logi c dq s0 ? dq s8 (sstl) negative and positive edge data strobe fo r in put and output d a ta dm0 ? dm8 input active high the data write m a sks, assoc i ated w i th on e data b y t e . in write mode, dm operat es as a b y te mask b y allow i ng input data to be w r itten if it is low but blocks the w r ite ope ratio n if it is high. in read mode, dm line s have no e ffect. dm8 is associate d w i th check bits cb0-cb7, an d is not used on x64 modules. reset (lvc-m os) active lo w sa0 ? sa2 - address inputs. connected to eit her v dd or v ss on the s y stem bo ard to configure t he serial presence detect eeprom address. sda - this bi-directional pin is used to transfer data into or out of th e spd eeprom. a resistor must be connected from the s d a bus line to v dd to act as a pullup. scl - this signal i s use d to clock data in to and out of t he spd eeprom. a resistor ma y b e connected from t he scl bus time to v dd to act as a pullup. v ddspd suppl y serial eeprom positive pow er s uppl y . rev 1.0 3 02/2003 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512 d72 s 8p abg 512mb : 64m x 72 pc210 0 unbuffered ddr dimm functional block diagram (2 bank, 32mx8 ddr sdrams) se r i a l pd a0 a2 a1 scl wp sda sa0 s a 2 sa1 3. dq/d qs /d m / d q s resi stor s are 22 oh m s . n o tes : 1. dq-to-i/o w r i n g m a y be ch anged w i thi n a byte. 2. dq/d qs /d m / c k e / s rel a ti onshi ps are m a i n tai ned a s show n. 4. v ddid strap co nnecti ons (fo r m e m o ry d e vi ce v dd , v dd q ): s t rap o u t ( o pen) : v dd = v ddq st ra p in (v ss ): v dd i s no t equal to v dd q . v ddspd v ss v ref v ddid v dd /v ddq s t rap : see note 4 spd d0 - d 8 d0 - d 8 d0 - d 8 a0 - a 1 3 ras ba0 - ba1 ba 0 - ba1 : sdr a m s d0 - d 1 7 a0 - a 1 3 : sdra m s d0 - d 1 7 ra s : s d ra m s d0-d17 c ke0 we ca s c as : sdram s d0 - d 1 7 ck e : sdram s d0 - d 8 ck e : sdram s d9 - d 1 7 we : sdram s d0 - d 1 7 c ke1 * w i r e per cl oc k load i ng t abl e/ w i r i ng di agr am s * cl ock w i r i ng c l oc k input sdram s *c k0 / ck0 *c k1 / ck1 *c k2 / ck2 6 sdram s 6 sdram s 6 sdram s s0 dm0 / dqs9 dq0 dq1 dq2 dq7 dq4 dq6 dq5 dq3 dq8 dq9 dq1 0 dq1 5 dq1 2 dq1 4 dq1 3 dq1 1 dq1 6 dq1 7 dq1 8 dq2 3 dq2 0 dq2 2 dq2 1 dq1 9 dq2 4 dq2 5 dq2 6 dq3 1 dq2 8 dq3 0 dq2 9 dq2 7 dqs0 dm 4 / dqs1 3 dqs4 dm 1 / dqs1 0 dqs1 dm 2 / dqs1 1 dqs2 dm 3 / dqs1 2 dqs3 dq3 2 dq3 3 dq3 4 dq3 9 dq3 6 dq3 8 dq3 7 dq3 5 dq4 0 dq4 1 dq4 2 dq4 7 dq4 4 dq4 6 dq4 5 dq4 3 dqs5 dm 5 / dqs1 4 dq4 8 dq4 9 dq5 0 dq5 5 dq5 2 dq5 4 dq5 3 dq5 1 dq5 6 dq5 7 dq5 8 dq6 3 dq6 0 dq6 2 dq6 1 dq5 9 dqs6 dm 6 / dqs1 5 dqs7 dm 7 / dqs1 6 s1 cb0 cb1 cb2 cb7 cb4 cb6 cb5 cb3 dm 8 / dqs1 7 dqs8 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d0 dq s i/ o 0 i/ o 1 i/ o 4 i/ o 3 i/ o 2 i/ o 7 i/ o 6 i/ o 5 dm cs d9 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d1 dq s i/ o 0 i/ o 1 i/ o 4 i/ o 3 i/ o 2 i/ o 7 i/ o 6 i/ o 5 dm cs d1 0 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d2 dq s i/ o 0 i/ o 1 i/ o 4 i/ o 3 i/ o 2 i/ o 7 i/ o 6 i/ o 5 dm cs d1 1 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d3 dq s i/ o 0 i/ o 1 i/ o 4 i/ o 3 i/ o 2 i/ o 7 i/ o 6 i/ o 5 dm cs d1 2 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d8 dq s i/ o 0 i/ o 1 i/ o 4 i/ o 3 i/ o 2 i/ o 7 i/ o 6 i/ o 5 dm cs d1 7 dqs i/ o 7 i/ o 6 i/ o 3 i/ o 4 i/ o 5 i/ o 0 i/ o 1 i/ o 2 dm cs d4 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d13 dqs i/ o 7 i/ o 6 i/ o 3 i/ o 4 i/ o 5 i/ o 0 i/ o 1 i/ o 2 dm cs d5 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d14 dqs i/ o 7 i/ o 6 i/ o 3 i/ o 4 i/ o 5 i/ o 0 i/ o 1 i/ o 2 dm cs d6 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d15 dqs i/ o 7 i/ o 6 i/ o 3 i/ o 4 i/ o 5 i/ o 0 i/ o 1 i/ o 2 dm cs d7 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d16 dqs rev 1.0 4 02/2003 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512 d72 s 8p abg 512mb : 64m x 72 pc210 0 unbuffered ddr dimm serial presence det ect -- part 1 of 2 64mx7 2 sdra m dimm based on 32mx8, 4b anks, 8k refre s h, 2.5v ddr sdrams w i th spd spd entry v a lue serial pd dat a e n try (hexadecimal) note by t e descr iption ddr266 -75t ddr266 -75t 0 number of se rial pd b y tes w r itte n during producti on 128 80 1 t o t a l numbe r of b y tes in serial pd device 256 08 2 fundament al memor y t y pe sdram ddr 07 3 number of ro w addresses on assembly 13 0d 4 number of colu mn addresses on assembly 10 0a 5 number of dimm bank 2 02 6 dat a wid t h of assembly x72 48 7 dat a wid t h of assembly (cont?) x72 00 8 v o lt age interface level of this assembl y sstl 2.5v 04 9 ddr sdram de vice cy cle t i me at cl=2.5 7.5ns 75 10 ddr sdram de vice a ccess t i me from clock at c l =2.5 0.75ns 70 1 1 d i m m configura t ion t y p e e c c 0 2 1 2 r e f r e s h rate/ t y p e sr/1x( 7 . 8 u s ) 8 2 13 primar y d dr sd ram wid t h x8 08 14 error checking ddr sdram devi ce wid t h x8 08 15 ddr sdram de vice attr: min clk dela y , ra ndo m col access 1 clock 01 16 ddr sdram de vice attributes: b u rst length supp orted 2,4,8 0e 17 ddr sdram de vice attributes: n u mber of d e vice banks 4 04 18 ddr sdram de vice attributes: c as latencies supported 2 04 19 ddr sdram de vice attributes: c s latenc y 0 01 20 ddr sdram de vice attributes: we latenc y 1 02 2 1 d d r sdram de vice attribut e s : d i f f e r e n t i a l c l o c k 2 0 22 ddr sdram de vice attributes: general +/-0.2v v o lt age t o lerance 00 23 minimum clock c y cle at cl=1.5 n/a 00 24 maximum dat a a ccess t i me from clock at cl=1.5 n/a 00 25 minimum clock c y cle t i me at cl =1 n/a 00 26 maximum dat a a ccess t i me from clock at cl=1 n/a 00 27 minimum row p r echarge t i me (t rp ) 1 5 n s 3 c 28 minimum row a c tive to row active dela y (t rr d ) 1 5 n s 3 c 29 minimum ras to cas dela y (t rcd ) 1 5 n s 3 c 30 minimum ras pulse wid t h (t ras ) 4 5 n s 2 d 31 module bank de nsity 256mb 40 32 address and co mmand setup t i me before clock 0.9ns 90 33 address and co mmand hold t i m e af ter clock 0.9ns 90 34 dat a input set u p t i me before clo ck 0.5ns 50 35 dat a input hold t i me af ter clock 0.5ns 50 3 6 - 6 1 r e s e r v e d u n d e f i n e d 0 0 6 2 s p d r e v i s i o n i n i t i a l 0 0 6 3 c h e c k s u m dat a 8 d rev 1.0 5 02/2003 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512 d72 s 8p abg 512mb : 64m x 72 pc210 0 unbuffered ddr dimm serial presence det ect -- part 2 of 2 64mx7 2 sdra m dimm based on 32mx8, 4b anks, 8k refre s h, 2.5v ddr sdrams w i th spd spd entry v a lue serial pd dat a e n try (hexadecimal) by t e descr iption ddr266 -75t ddr266 -75t note 64-71 manufacturer ? s jedec id code nan y a 7f7f7 f 0b00000 000 72 module manufact u ring location n/a 00 73-90 module part num ber n/a 00 9 1 - 9 2 m o d u l e revision c o d e n / a 0 0 93-94 module manufact u ring dat a y ear/w eek code yy/ ww 1, 2 95-98 module serial number serial number 00 9 9 - 2 5 5 r e s e r v e d undefined 00 1. yy= binar y code d decimal y e a r c ode, 0-99 (decimal), 00-63 (he x ) 2. ww = bina r y code d decimal y e a r c ode, 01-52 (decimal), 01-34 (he x ) rev 1.0 6 02/2003 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512 d72 s 8p abg 512mb : 64m x 72 pc210 0 unbuffered ddr dimm absolute maximum ratings s y m b o l p a r a m e t e r r a t i n g u n i t s v in , v out voltage on i/o pins relative to vss -0.5 to v ddq +0. 5 v v in voltage on input relative to vss -0.5 to +2.7 v v dd voltage on vdd supply relative to vss -0.5 to +2.7 v v ddq voltage on vdd q suppl y relative to vss -0.5 to +2.7 v t a oper ating temp erature (ambient ) 0 to +70 c t st g storage t e mper ature (plastic) -55 to +150 c p d pow e r dissipation 1 6 w i out short circuit out put cur r ent 5 0 m a note : stresses greater than thos e listed under ?a bsolute maximu m ratings? ma y cause permanen t dam age to the device. this is stress rating onl y, and functional operation of the d e vice at t hese or an y othe r conditions abov e those indicated in the operat ional sections of this specification is not im plied. exposure to absolute ma ximum rating co n d itions for extend ed periods ma y a ffect r eliability . cap a cit a n c e p a r a m e t e r s y m b o l max . u n i t s n o t e s input capacitance: ck0, ck0 , ck 1, ck1 , ck2, ck2 c i1 2 4 p f 1 input capacitance: a0-a12, ba0, ba1, we , ras , cas , cke0, s0 c i2 6 0 p f 1 input capacitance: sa0-sa2, sc l c i4 9 p f 1 input/ou t put cap a citance: dq0-6 3 ; dqs0 -7 c io1 1 4 p f 1 , 2 input/ou t put cap a citance: sda c io3 1 1 p f 1. v ddq = v dd = 2. 5v 0.2v, f = 10 0 mhz, t a = 25 c, v out (dc) = v ddq /2, v out (p eak to peak) = 0. 2v. 2. dq s inputs are g r ouped w i th i/ o p i ns reflecting the fact that the y are matched in loading to d q and d q s to facilitate trace matching at the boar d level. rev 1.0 7 02/2003 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512 d72 s 8p abg 512mb : 64m x 72 pc210 0 unbuffered ddr dimm dc electrical characteristics a nd operating conditions (t a = 0 c ~ 7 0 c; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v, see ac characteristics) s y m b o l p a r a m e t e r m i n m a x unit s n otes v dd s u p p l y voltage 2 . 3 2 . 7 v 1 v ddq i/o suppl y voltage 2.3 2.7 v 1 v ss, v ssq suppl y voltage, i / o suppl y v o ltage 0 0 v v ref i/o ref e rence v o ltage 0.49 x v ddq 0.51 x v ddq v 1 , 2 v tt i/o t e rmination voltage (s y s tem) v ref - 0.0 4 v ref + 0.04 v 1, 3 v ih (dc) input high (lo g ic1) voltage v ref + 0.15 v ddq + 0.3 v 1 v il (dc) input lo w (logic0) voltage -0.3 v ref - 0.1 5 v 1 v in (dc) input voltage le vel, ck and ck i nputs -0.3 v ddq + 0.3 v 1 v id (dc) input differential voltage, ck and ck inputs 0.30 v ddq + 0.6 v 1, 4 i i input leakage c u rrent an y input 0v v in v dd; (all other pins not under t e st = 0v) - 5 5 u a 1 i oz output l eakage curren t (dqs a r e disabled; 0v v out v dd q - 5 5 u a 1 i oh output high cur r ent (v out = v ddq -0. 373v, min v ref, min v tt ) - 1 6 . 8 - m a 1 i ol output l o w cu rr ent (v out = 0.373, max v ref , ma x v tt ) 1 6 . 8 - m a 1 1. inputs are not re cognized as valid until v ref stabili zes. 2. v ref is expected to be equal to 0. 5 v ddq of th e tr ansmitting device, and to tr ack variations in the dc level of the same. peak-to-peak noi se on v ref ma y not exceed 2 % o f the dc value. 3. v tt is not applie d directly to the dimm. v tt is a sy st em suppl y fo r signal termination resistors, is expected to be set equal to v ref, and must track variations in the dc level of v ref . 4. v id is the magnitude of the differ e nce bet w een the input level on ck and the input level on ck . rev 1.0 8 02/2003 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512 d72 s 8p abg 512mb : 64m x 72 pc210 0 unbuffered ddr dimm ac characteristics (notes 1-5 appl y to the follow i ng t ables; electrical c haracteristics and dc operating conditions, ac oper ating conditions, oper ating, standb y , a nd refresh c u rre nt s, and electrical charac teristics and ac timing.) 1. all voltages referenced to v ss . 2. tests for ac ti ming, i dd , and el ectrical, ac and dc characteri stics, ma y be condu cted at nominal r e ference/suppl y voltage levels, b u t the related specifications and device operation are guarantee d for th e full voltage range specified. 3. outpu t s measured w i th equivalent load. re fer to the ac output l oad circuit below. 4. ac timing and i dd tests ma y us e a v il to v ih s w i ng of up to 1.5v i n the test environ ment, but input ti ming is still referenced to v ref (o r to the crossing point for ck, ck ), and paramet er s pecifications are guarantee d for th e specified ac in put levels under normal use conditions. the minimum slew ra te for the i nput si gnals is 1v/ns in the range b e t w e en v il (ac) a nd v ih (ac) unless oth e r w ise specified. 5. the ac a nd d c input level specificat i ons are as defined in the s s tl_2 standa rd (i.e . the receiver effectively s w itches as a result of the signal crossing the ac input level, and remains in t hat state as long as the signal does not ring back above (belo w ) th e dc inp ut l o w ( h igh) level. ac output load circuit s ti m i n g ref e renc e p o i n t v tt 5 0 ohm s 30 pf o u t put v out ac operating conditions (t a = 0 c ~ 7 0 c; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v, see ac characteristics) s y mbol parameter/ condi tion min max unit notes v ih (ac) input high (lo g ic 1) voltage v ref + 0.31 - v 1, 2 v il (ac) input lo w (logic 0) voltage - v ref - 0.3 1 v 1, 2 v id (ac) input differential voltage, ck and ck inputs 0.7 v ddq + 0.6 v 1, 2, 3 v ix (ac) input differential pair cross point voltage, ck and ck inputs 0.5 x v dd q - 0. 2 0.5 x v dd q + 0.2 v 1, 2, 4 1. input slew rate = 1v/ ns. 2. inputs are not re cognized as valid until v ref stabili zes. 3. v id is the magnitude of the differ e nce bet w een the input level on ck and the input level on ck . 4. the value of v ix i s expected to eq ual 0.5 x v dd q of the transmitting device and must track va riations in the dc level of the same. rev 1.0 9 02/2003 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512 d72 s 8p abg 512mb : 64m x 72 pc210 0 unbuffered ddr dimm operating, standby , and refresh currents (t a = 0 c ~ 7 0 c; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v, see ac characteristics) s y mbol parameter/ condi tion pc2100 (-75 t ) unit notes i dd0 oper ating cur r e n t: one bank; active/precharge; t rc = t rc ( m in ); t ck = t ck (m i n ); d q , dm, a nd dqs inputs c hanging t w ice per clock cy cle; address and control input s changing once per clock cy cle 1 2 0 0 m a 1 , 2 i dd1 oper ating cur r e n t: one bank; active/read/precha rg e; burst = 2; t rc = t rc (m i n ); cl=2.5 ; t ck = t ck ( m i n ); i ou t = 0ma; address and control inputs changing once per clock cy cle 1 5 0 0 m a 1 , 2 i dd2p precharge po we r-do w n standb y curren t: all banks idle; pow er -do w n mode; cke v il (max); t ck = t ck ( m i n ) 4 2 0 m a 1 , 2 i dd2n idle standb y c u r r ent: cs v ih (m in ) ; all banks idle; cke v ih ( m i n ) ; t ck = t ck ( m in); addres s and control inputs changing once per clock cy cle 6 5 0 m a 1 , 2 i dd3p active pow e r- do w n st andb y cur r ent: one bank act i ve; pow e r-do w n mode; cke v il ( m a x ); t ck = t ck ( m in) 4 2 0 m a 1 , 2 i dd3n active standby c u rrent: one bank; active/precharge ; cs v ih ( m i n ); cke v ih ( m in); t rc = t r as ( m ax ) ; t ck = t c k ( m in) ; d q , dm, and dqs inputs changing tw ice p e r clock cy cle; addr ess and control inputs changing once per clock cy cle 8 6 0 m a 1 , 2 i dd4r oper ating cur r e n t: one bank; bur s t = 2; reads; continuous burst; a ddress and control input s changing once per clock cy cle; dq and dqs out puts changing tw ice p e r clock cy cle; cl = 2.5; t ck = t c k (min); i ou t = 0ma 2 4 0 0 m a 1 , 2 i dd4 w oper ating cur r e n t: one bank; bur s t = 2; writes; continuous burst; a ddress and control input s changing once per clock cy cle; dq and dqs inp u ts changing tw ice p e r clock cy cle; cl=2.5; t ck = t ck (m in ) 1 6 0 0 m a 1 , 2 i dd5 auto-refresh cu rrent: t rc = t rfc ( m i n ) 2000 ma 1, 2, 4 i dd6 self-refresh cu rrent: cke 0. 2v 5 4 m a 1 , 2 i dd7 oper ating cur r e n t: four bank; fo u r bank interleaving w i th bl = 4 , ad dress and control input s randoml y chan ging; 50% of da t a changing at ever y transfer; t rc = t rc (mi n ); i out = 0ma. 3 2 0 0 m a 1 , 2 1. i dd specification s are tested after the device is properl y initialized. 2. input slew rate = 1v/ ns. 3. enables on-chip refresh and addr ess counters. 4. curren t at 7.8 s is time-averaged value of i dd5 at t rfc ( m in) and i dd 2p over 7.8 s. rev 1.0 10 02/2003 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512 d72 s 8p abg 512mb : 64m x 72 pc210 0 unbuffered ddr dimm ac t i ming s p ecifications for d dr sdram devices used on module (t a = 0 c ~ 7 0 c; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v, see ac characteristics) (part 1 of 2 ) -75t s y mbol p a r a m e t e r m i n . m a x . unit notes t ac dq out put access time from ck/ ck - 0 . 7 + 0 . 7 n s 1 - 4 t dqsck dqs outp u t access time from ck/ ck - 0 . 7 + 0 . 7 n s 1 - 4 t ch ck high-level w i dth 0.45 0.55 t ck 1 - 4 t cl ck low-level w i dt h 0.45 0.55 t ck 1 - 4 t ck c l = 2 . 5 7 . 5 1 2 n s 1 - 4 t ck clock cy cle time c l = 2 7 . 5 1 2 n s 1 - 4 t dh dq and dm inpu t hold time 0.45 ns 1-4, 15, 16 t ds dq and dm inpu t setup time 0.45 ns 1-4, 15, 16 t dip w dq and dm inpu t pulse w i dth ( e a c h input) 1.75 ns 1-4 t hz data-out high -impedance time fro m ck/ ck - 0 . 7 + 0 . 7 n s 1 - 4 , 5 t lz data-out lo w-imp edance time fro m ck/ ck - 0 . 7 + 0 . 7 n s 1 - 4 , 5 t dqsq dqs- dq ske w ( d qs & associat ed dq signals) 0.45 ns 1-4 t hp minimum half clk period for a n y gi ven cy cle; defined b y clk high (t ch) or clk low ( t cl ) ti me t ch or t cl t ck 1 - 4 t qh data output h o ld time from d q s t hp - t qhs t ck 1 - 4 t qhs data hold ske w factor 0.55ns t ck 1 - 4 t dqss write command t o 1st dqs latching transition 0.75 1.25 t ck 1 - 4 t dqsl,h dqs input lo w (h igh) pulse w i dth (w rite c y cle) 0 . 3 5 t ck 1 - 4 t dss dqs falling edge to ck setup time (w rite c y cle) 0 . 2 t ck 1 - 4 t dsh dqs falling edge hold time from c k (w rite c y cle) 0 . 2 t ck 1 - 4 t mrd mode register se t command c y cle time 2 t ck 1 - 4 t wp r e s write preamble s e tup time 0 ns 1-4, 7 t wp s t w r i t e p o s t a m b l e 0 . 4 0 0 . 6 0 t ck 1 - 4 , 6 t wp r e w r i t e preamble 0 . 2 5 t ck 1 - 4 rev 1.0 11 02/2003 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512 d72 s 8p abg 512mb : 64m x 72 pc210 0 unbuffered ddr dimm ac timing specifications for d dr sdram devices used on module (t a = 0 c ~ 7 0 c; v ddq = 2.5v 0.2v; v dd = 2.5v 0.2v, see ac characteristics) (part 2 of 2 ) -75t s y mbol p a r a m e t e r m i n . m a x . unit notes t ih address and control input hold time (fast slew rate) 0 . 7 5 n s 2-4, 9, 11, 12 t is address and control input setup time (fast slew rate) 0 . 7 5 n s 2-4, 9, 11, 12 t ih address and control input hold time (s l o w s l e w rat e ) 0 . 8 n s 2-4, 10, 11, 12, 14 t is address and control input setup time (s l o w s l e w rate ) 0 . 8 n s 2-4, 10-12, 14 t ip w i n p u t pulse w i d t h 2 . 2 n s 2-4, 12 t rpre r e a d pre a m b l e 0 . 9 1 . 1 t ck 1-4 t rpst r e a d postamble 0 . 4 0 0 . 6 0 t ck 1-4 t ras active to precharge command 45 120,000 ns 1-4 t rc active to active/ a uto-ref r esh command period 60 ns 1-4 t rfc auto-ref r esh to a c tive/auto-refres h command period 7 5 n s 1 - 4 t rcd active to read or write dela y 15 ns 1-4 t rap active to read command w i th au toprecharge 15 ns 1-4 t rp precharge comm and period 15 ns 1-4 t rrd active bank a to active bank b co mmand 15 ns 1-4 t wr write recover y ti me 15 ns 1-4 t dal auto precharg e write recover y + precharge time (t wr /t ck ) + (t rp /t ck ) t ck 1 - 4 , 1 3 t wt r internal w r ite to r ead command d e la y 1 t ck 1 - 4 t pdex pow e r do wn exit time 7.5 ns 1-4 t xsnr exit self-refresh t o non-r ead com m and 75 ns 1-4 t xsrd exit self-refresh t o read command 200 t ck 1 - 4 t refi average periodic refresh inte rval 7.8 s 1-4, 8 rev 1.0 12 02/2003 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512 d72 s 8p abg 512mb : 64m x 72 pc210 0 unbuffered ddr dimm ac timing specification notes 1. input slew rate = 1v/ns. 2. the ck/ ck inp u t refer ence level (for timing refe re nce to ck/ ck ) is the point at w h ich ck and ck cro ss: the input refe rence level for signals other than ck/ ck is v ref . 3. inputs are no t recognized as valid until v ref sta b ilize s . 4. the output ti ming reference l e vel, as measured at the timing re ference point indicated in ac char acteristics (note 3) is v tt. 5. t hz and t lz transitions occur in the same access time w i ndo w s as va lid data transitions. these parameters a r e not refer r ed to a specific voltage level, but specify w h en the device is no longer driving (hz ) , or begin s driving (lz). 6. the ma ximum limit for this parameter is not a de vice limi t. the device operates w i t h a greate r value for this paramet er, but sy s t e m performa n ce (bu s turnaround ) de grades according l y . 7. the specific requirement is that dqs be valid (hi gh, low , or some point on a valid transition) on or b e fore this ck ed ge. a valid transition is defin ed as monotonic and meeting the i nput slew rate sp ecification s of the device. when no w r ites w e re pr eviously in pr ogr ess on the bus, dq s w ill be tr ansitioning fr om hi- z to logic low. if a pr evious wr ite w a s in pr ogr e ss, dq s could be high, lo w, or transitioning fr om high to lo w at this time, depending on tdqss. 8. a maximum of eight auto refr esh commands can be posted to an y given ddr sdr a m device. 9. for comman d / address input slew rate >= 1.0 v/n s . slew rate is measured bet w e en v oh (ac) and v ol (ac). 10. for comma n d /address input slew r a te >= 0.5 v / ns and < 1.0 v/n s . slew rate is measured bet w e en v oh (ac) and v ol (ac). 11. ck/ ck sle w r a tes are >= 1.0 v / ns. 12. these pa ram e ters guaran tee device timing, bu t the y a r e not n e c essarily tested on each device, and the y ma y be guarantee d b y design or tester c haracterization. 13. for each of t he terms in pare n theses, if not alread y an inte g e r, round to th e ne xt highest integer. t ck is equal to the ac tual sy stem clock cy cle time. for e x ample, fo r pc2100 at cl= 2. 5, t dal = (1 5n s/7.5ns) +(20ns/ 7 .0ns) = 2 + 3 = 5. 14. an input setu p and hold time d e rating tabl e is used to increase t is and t ih in the case w h e r e the i nput slew rate is belo w 0 . 5 v/ns. input slew rate delta (tis ) d e l t a (tih ) u n i t n o t e 0.5 v/ns 0 0 ps 1, 2 0.4 v/ns +50 0 ps 1, 2 0.3 v/ns +100 0 ps 1, 2 1. input slew rate is based on the lesser of the sle w ra tes determined b y either v ih ( a c ) to v il (ac) or v i h (dc) to v i l (dc), s i mi l a rl y for rising transitions. 2. these derating p a rameters ma y b e guarante ed b y design or test er c haracterization a nd are not necessarily tested o n e a ch devi ce. 15. an input setu p and hold time d e rating table is used to increas e t ds and t dh in t he case w h e r e th e i/o sle w rat e is below 0.5 v/ns. input slew rate delta (tds ) d e l t a (tdh ) u n i t n o t e 0.5 v/ns 0 0 ps 1, 2 0.4 v/ns +75 +75 ps 1, 2 0.3 v/ns +150 +150 ps 1, 2 1. i/o sle w rate is b a sed on the lesser of the sle w ra t e s determined b y either v ih (a c) to v il (ac) or v ih (dc) to v il (dc), s i mi l a rl y for rising transitions. 2. these derating p a rameters ma y b e guarante ed b y design or test er c haracterization a nd are not necessarily tested o n e a ch devi ce. 16. an i/o delta rise, fall derating table is used to increase t ds an d t dh in the cas e where dq, dm , and d q s slew r a tes diffe r. delta rise and f a ll rate delta (tds ) d e l t a (tdh ) u n i t n o t e 0.0 ns/v 0 0 ps 1-4 0.25 ns/v +50 +50 ps 1-4 0.5 ns/v +100 +100 ps 1-4 1. input slew rate is based on the lesser of the sle w ra tes determined b y either v ih ( a c ) to v il (ac) or v i h (dc) to v i l (dc), s i mi l a rl y for rising transitions. 2. input slew rate is based on the lar ger of ac to a c delta rise, fall rate and dc to dc delta rise, fall rate. 3. the delta rise, fal l rate is calculate d as: [1/(slew rat e 1)] - [1 /(sle w ra te 2)] for e x ample: slew rate 1 = 0. 5 v/ ns; slew rate 2 = 0.4 v/ns. delta ri se, fall = (1/0.5) - (1/0.4) [ n s/v] = - 0 .5 ns/v using the table above, this w ould result in an increase in t ds and t dh of 100 ps. 4. these derating p a rameters ma y b e guarante ed b y design or test er c haracterization a nd are not necessarily tested o n e a ch devi ce. rev 1.0 13 02/2003 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512 d72 s 8p abg 512mb : 64m x 72 pc210 0 unbuffered ddr dimm packag e dimensions 133.35 128.9 5 1.2 5 0 0.157 0.700 fr o n t side 0.394 1. 27+ /- 0.10 d e t a il a 1.27 p i tch d e t a il b 1.00 w i dth 4.00 d e t a il a d et a il b 0 . 091 (2 ) 2. 50 3.80 1. 80 6.35 5.25 5.07 7 2.30 (2x)4.00 17.80 31 .75 10.0 0. 098 0.15 7 m a x . 0.05 0 + / - 0.004 0.05 0.039 0 . 071 0.250 0.150 4.00 0.157 back not e : a l l di m ens i ons are t y pi c a l w i t h t o l e ra nc es of +/ - 0. 15 (0. 006 ) unl es s ot h e rw i s e s t at ed. u n its: m i llim e t e r s ( i nch e s ) rev 1.0 14 02/2003 ? n a n y a te chnol ogy corp . n a ny a t e ch nology c o rp . r e s e r v e s the r i ght to c h a nge p r oduc t s a nd s p e c i fic a t ions w i thout notic e .
nt512d72s8pabg 512mb : 64m x 72 pc2100 unbuffered ddr dimm rev 1.0 15 02/2003 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. revision log rev date modification 0.1 11/2002 preliminary release updated operating, standby, and refresh currents table 1.0 02/2003 final release

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